Challenges to Providing Performance Isolation in Transactional Memories

Due to the inevitability of chip multiprocessors and the difficulty of parallel software development, there has been widespread interest in techniques that facilitate parallel programming. Recently, there have been a number of proposals regarding hardware support for transactional programming models. A key advantage of transactional programming models over lock-based synchronization is that two critical sections may be executed in parallel if they do not conflict, without the programmer needing to implement fine-grain locking. In effect, transaction hardware provides an implicit system-wide lock that is speculatively elided. In this paper, we identify three factors that allow one process to impact the performance of other concurrently running, independent processes to a degree not present in traditional (non-transactional) multiprocessors: (1) forward progress is defined in terms of user-specified transactions (rather than instructions), (2) inefficiencies in verifying the independence of critical sections with large data footprints, and (3) subsumption of kernel execution in user-mode transactions. We describe and discuss specific problematic scenarios in the context of existing transactional hardware proposals. We believe these scenarios should be considered in architecting a robust transactional-based system.